Portable information apparatuses including a multimedia processing function such as an image or a voice and wire and radio communicating functions have generally been utilized widely, and an enhancement in performance, an improvement in a function and a reduction in a consumed power in a data processor have been required in order to provide these apparatuses inexpensively in small sizes. On the other hand, a quick correspondence to various specifications and standards decided together with the progress of a development of a technology greatly depends on the value of a product. Therefore, the function can easily be changed or added by software after the manufacture of the apparatus so that it is possible to shorten a product development period, and furthermore, to prolong the lifetime of the product.
As first means for implementing the data processor, there is a method of designing a dedicated logical circuit capable of carrying out a prepared and limited change in the function as in a plurality of operating modes and mounting a dedicated LSI combining them. The dedicated LSI can be generally supposed to be the most excellent implementing means in respect of an achievement of an enhancement in a performance and a reduction in a consumed power. However, the method is selected as the implementing means with difficulty because the function can neither changed nor added until the dedicated LSI is not designed again and a long development period is required for the design.
As second means, there is a method of mounting a general-purpose microprocessor and implementing various processings by software including a serial instruction string to be executed over the processor. In this case, it is possible to modify or add the software, thereby enhancing a function and changing and adding the function without varying the hardware of a data processor. Also in a leading edge microprocessor, however, several instructions can be executed at the same time. In order to implement a processing having a high throughput in a data processor based on a sequential processing of an instruction, it is necessary to mount a processor to be operated at a very high clock frequency. Consequently, a consumed power is increased. In order to bring out the processing performance of the processor, furthermore, a control logic other than a calculation, for example, a branch prediction is required. Consequently, there is a drawback that a logic scale of a calculator body is relatively reduced, resulting in a decrease in a processing efficiency for the hardware scale.
As more actual implementing means corresponding to the middle of these two means, in recent years, attention has been paid to a reconfigurable LSI which is referred to as a Field Programmable Gate Array (FPGA) and a coverage has been enlarged gradually. The FPGA has an internal structure in which a large number of Lookup Tables (LUTs) are connected to each other through a bus having a path which can be changed and has a feature that the contents of the operation of the LUT and configuration data for defining a connection between the LUTs are read from a memory attached externally to the LSI and an optional function can be thus implemented in the LSI. Basically, the contents of the operation of the LUT and the connection between the LUTs can be set on a 1-bit unit. Therefore, a flexibility is high in the implementation of a predetermined function over the LSI. On the other hand, there is a problem in that an area overhead is great in an application field in which a multibit calculation such as an image and voice processing is mainly carried out.
In consideration of such a technical background, there has been well-known a flexible processor technique which comprises a calculator for setting a calculation of a fineness degree in a width of approximately 8 to 32 bits to be a unit and is intended for balancing a calculating performance with a flexibility in a high dimension, and the same technique has been described in Patent Document 1 (JP-A-2001-312481 Publication) and Patent Document 2 (JP-A-2004-040188 Publication), for example. The FPGA has a logical gate of an NAND or NOR circuit disposed in an array and a connection wiring thereof is switched. On the other hand, in the flexible processor technique, a calculating unit is disposed in an array in place of the logical gate, and a function of the calculating unit and a wiring between the calculating units are switched based on configuration data.